Journal Articles

  • Kobayashi, Ryoji and Nguyen, Ngo Doanh and A. B. Abdallah and Nguyen, Anh Vu Doan and Dang, Nam Khanh, “ApproxiMorph: Energy-efficient Neuromorphic System with Layer-wise Approximation of Spiking Neural Networks and 3D-Stacked SRAM”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), doi: 10.1109/TCAD.2025.3597251.

  • Nguyen, Ngo Doanh and Dang, Nam Khanh and A. B. Ahmed and A. B. Abdallah and Tran, Xuan Tu, “NOMA: A Novel Reliability Improvement Methodology for 3-D IC-based Neuromorphic Systems,” in IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), doi: 10.1109/TCPMT.2024.3488113.

  • Dang, Nam Khanh and Nguyen, Anh Vu Doan and Nguyen, Ngo Doanh and A. B. Abdallah, “HeterGenMap: An Evolutionary Mapping Framework for Heterogeneous NoC-based Neuromorphic Systems,” in IEEE Access, doi: 10.1109/ACCESS.2023.3345168.

  • Nguyen, Ngo Doanh and A. B. Ahmed and A. B. Abdallah and Dang, Nam Khanh, “Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2023.3318231.

  • Nguyen, Ngo Doanh and Tran, Xuan Tu and A. B. Abdallah and Dang, Nam Khanh, “An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture,” in IEEE Access, vol. 11, pp. 82377-82389, 2023, doi: 10.1109/ACCESS.2023.3301560.

Conference Papers

  • Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu and Orazio, Aiello, “Comparison between Gate-driven CMFBs on Inverter-based OTAs in Multiple Specifications”, in 2025 5th IEEE International Circuit and System Symposium (ICSyS), 24-26 November 2025, Everly Putrajaya, Malaysia.

  • The-Anh Nguyen, Thao-Nguyen Tran-Ha, Ngo-Doanh Nguyen, Khanh N. Dang, Duy-Hieu Bui, and Xuan-Tu Tran, “An Efficient Hardware Compression Technique for Low-Power Spiking Neural Networks,” in 2025 24th International Symposium on Communications and Information Technologies (ISCIT), 16-18 October 2025, Hanoi, Vietnam.

  • Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu and Orazio, Aiello, “0.3V Specification-oriented Inverter-based OTAs with NAND-and-NOR CMFB using Different Standard Cells’ Strength,” in 21st IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 12-15 October 2025, Busan, Korea.

  • Riccardo, Della Sala and Orazio, Aiello and Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu and Giuseppe, Scotti, “Exploring 0.3V Inverter Based OTA Designs with NOR3-Based Common Mode Feedback,” in 2025 IEEE 23rd Interregional NEWCAS Conference, June 22-25, 2025, Paris, France.

  • Kobayashi, Ryoji and Nguyen, Ngo Doanh and Nguyen, Anh Vu Doan and Dang, Nam Khanh, “A Low-power Spiking Neural Network Using Approximate Neuron Circuit and Approximate Stacking Memory,” in 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), December 16-19, 2024, Kuala Lumpur, Malaysia.

  • Nguyen, Ngo Doanh and Dang, Nam Khanh, “A Novel Yield Improvement Approach for 3D Stacking Neuromorphic Architecture,” in 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), December 18-21, 2023, Singapore, Singapore.

  • Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu, “Tiny Neuron Network System based on RISC-V Processor: A Decentralized Approach for IoT Applications”. In 2022 International Conference on Advanced Technology for Communication (ATC), 20-22 October 2022, Hanoi, Vietnam.

  • Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu, “An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection”. In 2022 International Conference on IC Design and Technology (ICICDT), 21-23 September 2022, Hanoi, Vietnam.

  • Tran, Duc Manh and Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu, “A Highly Digital VCO-based ADC for IoT Applications on Skywater 130nm”. In NAFOSTED Conference on Information and Computer Science (NISC), December 21-22, 2021, Hanoi, Vietnam.

  • Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu, “A Lightweight AEAD encryption core to secure IoT applications”. In 16th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 8-12 December 2020, Ha Long, Vietnam.

  • Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu, “A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization”. In 15th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 11-14 November 2019, Bangkok, Thailand.

Patents

  • Dang, Nam Khanh and Ben Abdallah, Abderazek and Nguyen, Ngo Doanh, “Neural Network Processor”, Special Application 2024-047372, Japan patent, March 2024, Japan (Pending).

  • Tran, Xuan Tu and Bui, Duy Hieu and Nguyen, Ngo Doanh, “Methodology of Hardware/Software Co-processing of the Authenticated Encryption with Associated Data algorithm, AES-GCM, for energy-efficiency IoT devices”, Vietnamese Patent, 1-2021-05898, 2025, Vietnam.

  • Tran, Xuan Tu and Bui, Duy Hieu and Nguyen, Ngo Doanh, “Methodology of Hardware/Software Co-processing of the Authenticated Encryption with Associated Data algorithm, AES-CCM, for energy-efficiency IoT devices”, Vietnamese Patent, 1-2021-01093, 2025, Vietnam.

Book Chapters

  • Nguyen, Ngo Doanh and Dang, Nam Khanh and Ben Abdallah, Abderazek and A. B. Ahmed, “Chapter 9: Low-Power 3-D IC-Based Spiking Neural Network”, in “Energy-Efficient Devices and Circuits for Neuromorphic Computing”, Elsevier, 2025, 978-0-443-29981-0, B978-0-443-29981-0.00007-0, doi: 10.1016/B978-0-443-29981-0.00007-0.